The technology of microcomputer architecture and design has made incredible advances in the past several decades. New architectural ideas combined with advances in integrated circuit technology have combined to create a series of machines which achieve remarkable performance results.
One way that computer architects can further improve the performance of their machines is by measuring and monitoring the various parameters that affect the performance of the processor. For example, by measuring the system performance of the machine when it is executing its intended applications, the computer architect is better assisted in his effort to design a balanced computer system.
In the past, system architects and designers typically relied upon logic analyzers and other external hardware to generate statistical information concerning the operation of a computer. Most often, this type of information was gathered from huge mainframe computers. However, because the processing unit (CPU) is a single integrated circuit, it is largely inaccessible. The internal operation of microprocessors has generally remained a so-called "black box" mystery. Lack of a means for obtaining statistics on the operation of CPUs has impeded further advances in computer design; this information would also be useful for both compiler and system memory tuning.
What is needed then is a means for monitoring the performance of a microprocessor by obtaining statistical information produced by the central processing unit. As will be seen, the present invention comprises an apparatus for measuring and monitoring various parameters that contribute to the performance of a microprocessor. One of the advantages of the present invention is that it makes it possible to measure such parameters as data and instruction cache hit rates, clocks per instruction (CPI), time spent waiting for external bus functions, etc. The performance monitor of the present invention also allows compiler writers to gauge the effectiveness of instruction scheduling algorithms by measuring address generation interlocks and parallelism.